Reconfiguration and Adaptation
This simulation needs to run faster!
Use GPUs! Everyone does.
Well, they are not flexible enough.
Not every program can be
accelerated on a GPU.
How about FPGAs?
They are too complex to program
and achieve only low clock
frequencies.
And ASICs?
Way too expensive!
It is a great challenge for software engineers to write performant code. They put in a lot of effort
to make sure that the users of the software get their work done as fast as possible. This can be sophisticated
simulations, complex numerical calculations or even database queries.
Here, the choice of the computer architecture is crucial. However, in many cases traditional hardware designs are either not flexible
enough (GPUs), not fast enough (FPGAs) or too expensive (ASICs).
Our Reconfigurable Compute Engine (RCE) is the solution to
this problem. This reconfigurable chip can adapt to any software (more flexible than GPUs) to achieve optimal
performance (faster and easier to program than FPGAs) and low energy consumption without the need of customized hardware, keeping the cost
down (cheaper than ASICs).
Just like a chameleon, our RCE fits in everywhere to accelerate software execution through reconfiguration and adaptation.
Dr.-Ing. Lukas Jung
Software Development
Lukas Jung is an expert in hardware reconfiguration and accelerators. In 2019 he finished his PhD in this area with
Summa cum Laude. On the IPDPS 2016 he was awarded the Best Poster Recognition Award for his contribution "Coarse Grained
Reconfigurable General Purpose Hardware Accelerators".
Dr.-Ing. Changgong Li
Hardware Development
Changgong Li is an expert in hardware development.
During his PhD he implemented a prototype of the first Java-Processor that is able to
execute the whole SPEC benchmark suite. This processor is based on the novel Adaptive Mircoinstruction Driven Architecture (AMIDAR)
which differs completely from common computer architectures.
Prof. Dr.-Ing. Christian Hochberger
Mentor
Christian Hochberger leads the Computer Systems Group at Technische Universität Darmstadt
and has 20 years of experience in the research of reconfigurable computer architectures.
He is the inventor of the reconfigurable AMIDAR processor
Prof. Dr.-Ing. Peter Thoma
Advisor
Peter Thoma led the R&D division of the CST AG (Computer Simulation Technology) for almost 20
years as Managing Director. Now he is
Senior Director R&D Technology at Dassault Systèmes and is Professor for simulation methods
at the Computer Science and Engineering faculty at Frankfurt University of Applied Sciences.
Chameleon Acceleration Systems was funded by the Federal Ministry for Economic Affairs and Energy (BMWi)
and the European Social Fund (ESF) within the context of the EXIST funding program from September 2020 to August 2021
Our Reconfigurable Compute Engine (RCE) consists of multiple processing elements (PE) whose interconnect can be reconfigured. All PEs can
either work together synchronously on one large problem or groups of PEs handle different threads or even different
problems in parallel. That way it is possible to exploit parallelism on instruction level, thread level and task level.
PEs that cannot carry out a meaningful task, will be switched off to save energy.
Still, the RCE can be used with low overhead: Software providers compile their software
with our special LLVM-based compiler. This compiler automatically generates configuration files for the RCE and inserts
the corresponding call methods in the software application
The RCE itself is provided to the user of the software as an add-in board that can be inserted in
any workstation or server with PCIe connectors. During software execution the desired configurations are loaded into
the RCE and the running application can make use of RCE's computing power.
Performance critical parts of the application will be executed on the RCE which leads to
increased performance and less energy consumption.
